Compiler instructions for vector transfer unit

ABSTRACT

A compiler and vector data transfer instructions for use in a vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. The compiler identifies the use of vector data in an application program and implements one or more vector instructions for transferring the vector data between memory and registers used to perform calculations on the vector data. A vector is partitioned by the compiler into variable-sized streams which are transferred into and out of the processor as burst transactions. The compiler schedules transfers of vector streams required in a calculation so that calculations on a portion of the vector data are performed while a subsequent portion of the vector data is transferred. A vector buffer pool is partitioned into one or more vector buffers and each vector buffer is used at a specific time. The compiler partitions a vector buffer into the variable-sized streams depending on the number of vectors buffers required by an application program and the size required for each stream. Each vector buffer is allocated for exclusive use by an application program that is executing in the data processor. A synchronization instruction is used to allow all VTU instructions issued prior to the synchronization instruction to finish before any VTU instructions issued after the synchronization instruction may begin. Instructions for controlling access to the vector buffer pool are also included.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to special purpose memory integrated ingeneral purpose computer systems, and specifically to a memory systemfor efficient handling of vector data.

2. Description of the Related Art

In the last few years, media processing has had a profound effect onmicroprocessor architecture design. It is expected that general-purposeprocessors will be able to process real-time, vectored media data asefficiently as they process scalar data. The recent advancements inhardware and software technologies have allowed designers to introducefast parallel computational schemes to satisfy the high computationaldemands of these applications.

Dynamic random access memory (DRAM) provides cost efficient main memorystorage for data and program instructions in computer systems. Staticrandom access memory (SRAM) is faster (and more expensive) than DRAM andis typically used for special purposes such as for cache memory and databuffers coupled closely with the processor. In general a limited amountof cache memory is available compared to the amount of DRAM available.

Cache memory attempts to combine the advantages of quick SRAM with thecost efficiency of DRAM to achieve the most effective memory system.Most successive memory accesses affect only a small address area,therefore the most frequently addressed data is held in SRAM cache toprovide increase speed over many closely packed memory accesses. Dataand code that is not accessed as frequently is stored in slower DRAM.Typically, a memory location is accessed using a row and column within amemory block. A technique known as bursting allows faster memory accesswhen data requested is stored in a contiguous sequence of addresses.During a typical burst, memory is accessed using the starting address,the width of each data element, and the number of data words to access,also referred to as “the stream length”. Memory access speed is improveddue to the fact there is no need to supply an address for each memorylocation individually to fetch or store data words from the properaddress. One shortfall of this technique arises when data is not storedcontiguously in memory, such as when reading or writing an entire row ina matrix since the data is stored by column and then by row. It istherefore desirable to provide a bursting technique that can accommodatedata elements that are not contiguous in memory.

Synchronous burst RAM cache uses an internal clock to count up to eachnew address after each memory operation. The internal clock must staysynchronized with the clock for the rest of the memory system for fast,error-free operation. The tight timing required by synchronous cachememory increases manufacturing difficulty and expense.

Pipelined burst cache alleviates the need for a synchronous internalclock by including an extra register that holds the next piece ofinformation in the access sequence. While the register holds theinformation ready, the system accesses the next address to load into thepipeline. Since the pipeline keeps a supply of data always ready, thisform of memory can run as fast as the host system requests data. Thespeed of the system is limited only by the access time of the pipelineregister.

Multimedia applications typically present a very high level ofparallelism by performing vector-like operations on large data sets.Although recent architectural extensions have addressed thecomputational demands of multimedia programs, the memory bandwidthrequirements of these applications have generally been ignored. Toaccommodate the large data sets of these applications, the processorsmust present high memory bandwidths and must provide a means to toleratelong memory latencies. Data caches in current general-purpose processorsare not large enough to hold these vector data sets which tend topollute the caches very quickly with unnecessary data and consequentlydegrade the performance of other applications running on the processor.

In addition, multimedia processing often employs program loops whichaccess long arrays without any data-dependent addressing. These programsexhibit high spatial locality and regularity, but low temporal locality.The high spatial locality and regularity arises because, if an arrayitem n is used, then it is highly likely that array item n+s will beused, where “s” is a constant stride between data elements in the array.The term “stride” refers to the distance between two items in data inmemory. The low temporal locality is due to the fact that an array itemn is typically accessed only once, which diminishes the performancebenefits of the caches. Further, the small line sizes of typical datacaches force the cache line transfers to be carried out through shortbursts, thereby causing sub-optimal usage of the memory bandwidth. Stillfurther, large vector sizes cause thrashing in the data cache. Thrashingis detrimental to the performance of the system since the vector dataspans over a space that is beyond the index space of a cache.Additionally, there is no way to guarantee when specific data will beplaced in cache, which does not meet the predictability requirements ofreal-time applications. Therefore, there is a need for a memory systemthat handles multi-media vector data efficiently in modern computersystems.

SUMMARY OF THE INVENTION

The present invention is utilized in an extension to a computer systemarchitecture to improve handling of vector data. The extension providesa compiler-directed memory interface mechanism by which vector data setscan be transferred efficiently into and out of the processor under thecontrol of the compiler. Furthermore, the hardware architecturalextension of the present invention provides a mechanism by which acompiler can pipeline and overlap the movement of vector data sets withtheir computation.

Accordingly, one aspect of the present invention provides a vectortransfer pipelining mechanism which is controlled by a compiler. Thecompiled program partitions its data set into streams, also referred toas portions of the vector data, and schedules the transfer of thesestreams into and out of the processor in a fashion which overlaps thedata transfers and the required computation. To perform an operationsuch as y=f(a,b) in which a, b, and y are all large vectors, thecompiler partitions vectors a, b, and y into segments. These vectorsegments can be transferred between the processor and the memory asseparate streams using a burst transfer technique. The compilerschedules these data transfers in such a way that previous computationresults are stored in memory, and future input streams are loaded in theprocessor, while the current computation is being performed.

The compiler detects the use of vector data in application programs,(for example, loops through matrices), schedules read and write streamsto memory, and maintains synchronization with the computation. Oneembodiment of the present invention includes the use of a vector dataindicator that the compiler may use to recognize the use of vector data.

An important aspect of the present vector transfer unit (VTU) is thatthe vector streams bypass the data cache when they are transferred intoand out of the processor. The compiler partitions vectors intovariable-sized streams and schedules the transfer of these streams intoand out of the processor as burst transactions.

A vector buffer is a fixed-sized partition in the vector buffer pool(VBP) which is normally allocated to a single process and is partitionedby the compiler among variable-sized streams each holding a vectorsegment.

Data is transferred into and out of the VBP using special vector datainstructions. One set of instructions perform the transfer of databetween the memory and the vector buffers. Another pair of instructionsmove the data between the vector buffers and the general-purposeregisters (both integer and floating-point registers). The processoruses the vector data directly from the registers.

A synchronization instruction is used to synchronize accessing thevector data with processing the vector data, and forces all VTUinstructions fetched prior to the synchronization instruction to finishbefore any VTU instruction issued after the synchronization instructionmay begin.

One or more of the vector instructions includes information required totransfer a vector stream including the memory starting address of thestream, the starting address of the buffer, the length, and the strideof the vector stream, and the width of the vector data in the datastream.

The vector instruction may also include information about whether thevector data is integer or floating point data.

In one embodiment of the present invention, one application program at atime may access the vector buffer pool and vector transfer instructionqueue. Accordingly, one or more vector instructions are used todetermine whether the buffer pool is available for use by anotherapplication program.

The foregoing has outlined rather broadly the objects, features, andtechnical advantages of the present invention so that the detaileddescription of the invention that follows may be better understood.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a computer system.

FIG. 2 is a diagram of a vector transfer unit in accordance with thepresent invention.

FIG. 3 is a diagram showing memory partitioned into various segmentshaving different privilege access levels, cache characteristics, andmapping characteristics.

FIG. 4 is a diagram of an embodiment of a configuration register inaccordance with the present invention.

FIG. 5 shows a state diagram for managing a vector buffer pool during acontext switch in accordance with the present invention.

FIG. 6 a shows an example of data transfer requirements with unpackeddata elements.

FIG. 6 b shows an example of data transfer requirements with packed dataelements using a packing ratio of two.

FIG. 7 shows a timing diagram for a variable-length vector burst.

The present invention may be better understood, and its numerousobjects, features, and advantages made apparent to those skilled in theart by referencing the accompanying drawings. The use of the samereference symbols in different drawings indicates similar or identicalitems.

DETAILED DESCRIPTION

FIG. 1 illustrates a computer system 100 which is a simplified exampleof a computer system with which the present invention may be utilized.It should be noted, however, that the present invention may be utilizedin other computer systems having an architecture that is different fromcomputer 100. Additionally, the present invention may be implemented inprocessing systems that do not necessarily include all the featuresrepresented in FIG. 1.

Computer system 100 includes processor 102 coupled to host bus 104.External cache memory 106 is also coupled to the host bus 104.Host-to-PCI bridge 108 is coupled to main memory 110, includes cachememory 106 and main memory 110 control functions, and provides buscontrol to handle transfers among PCI bus 112, processor 102, cachememory 106, main memory 110, and host bus 104. PCI bus 112 provides aninterface for a variety of devices including, for example, LAN card 114.PCI-to-ISA bridge 116 provides bus control to handle transfers betweenPCI bus 112 and ISA bus 114, IDE and universal serial bus (USB)functionality 120, and can include other functional elements not shown,such as a real-time clock (RTC), DMA control, interrupt support, andsystem management bus support. Peripheral devices and input/output (I/O)devices can be attached to various I/O interfaces 122 coupled to ISA bus114. Alternatively, many I/O devices can be accommodated by a super I/Ocontroller (not shown) attached to ISA bus 114. I/O devices such asmodem 124 are coupled to the appropriate I/O interface, for example aserial interface as shown in FIG. 1.

BIOS 126 is coupled to ISA bus 114, and incorporates the necessaryprocessor executable code for a variety of low-level system functionsand system boot functions. BIOS 126 can be stored in any computerreadable medium, including magnetic storage media, optical storagemedia, flash memory, random access memory, read only memory, andcommunications media conveying signals encoding the instructions (e.g.signals from a network). When BIOS 126 boots up (starts up) computersystem 100, it first determines whether certain specified hardware incomputer system 100 is in place and operating properly. BIOS 126 thenloads some or all of operating system 128 from a storage device such asa disk drive into main memory 110. Operating system 128 is a programthat manages the resources of computer system 100, such as processor102, main memory 110, storage device controllers, network interfacesincluding LAN card 114, various I/O interfaces 122, and data busses 104,112, 114. Operating system 128 reads one or more configuration files 130to determine the type and other characteristics of hardware and softwareresources connected to computer system 100.

During operation, main memory 110 includes operating system 128,configuration files 130, and one or more application programs 132 withrelated program data 134. To increase throughput in computer system 100,program data 134 and instructions from application programs 132 may beplaced in cache memory 106, and 136 determined by the pattern ofaccesses to both data and instructions by the application. Cache memoryis typically comprised of SRAM which has relatively fast access timecompared to other types of random access memory.

As shown in FIGS. 1 and 2, processor 102 includes internal cache memory136 and VTU 138. Internal cache memory 136 is built into processor 102'scircuitry and may be divided functionally into separate instructioncaches (I-caches) 202 and data caches (D-caches) 204 where I-cache 202stores only instructions, and D-cache 204 holds only data. VTU 138 isintegrated in processor 102 and includes vector transfer execution unit206, vector buffer pool (VBP) 208, and an efficient bus protocol whichsupports burst transfers.

While main memory 110 and data storage devices (not shown) such as diskdrives and diskettes are typically separate storage devices, computersystem 100 may use known virtual addressing mechanisms that allowprograms executing on computer system 100 to behave as if they only haveaccess to a large, single storage entity, instead of access to multiple,smaller storage entities (e.g., main memory 110 and mass storage devices(not shown)). Therefore, while certain program instructions reside inmain memory 110, those skilled in the art will recognize that these arenot necessarily all completely contained in main memory 110 at the sametime. It should be noted that the term “memory” is used herein togenerically refer to the entire virtual memory of computer system 100.

Processor 102 operates in both 32-bit and 64-bit addressing modes inwhich a virtual memory address can be either 32 or 64 bits,respectively. Memory may be accessed in kernel, supervisor, and usermemory address access modes. Depending on the addressing mode, the32-bit or 64-bit virtual address is extended with an 8-bit address spaceidentifier (ASID). By assigning each process a unique ASID, computersystem 100 is able to maintain valid translation look-aside buffer (TLB)state across context switches (i.e., switching execution of one programto another in memory). The TLB provides a map that is used to translatea virtual address to a physical address.

Privilege Levels

Memory may be placed in protected virtual address mode with one or moredifferent levels of privileged access. An active program can access datasegments in memory that have a privilege level the same as or lower thanthe current privilege level. In one type of computer system with whichthe present invention may be utilized, there are three levels ofprivilege, denoted as kernel, supervisor, and user addressing modes. Thekernel of an operating system typically includes at least programs formanaging memory, executing task context switches, and handling criticalerrors. The kernel has the highest privilege level to help preventapplication programs 132 from destroying operating system 128 due toprogramming bugs, or a hacker from obtaining unauthorized access todata. Certain other operating system functions such as servicinginterrupts, data management, and character output usually run at a lowerprivilege level, often referred to as supervisor level. An even lowerprivilege level is assigned to application programs 132, therebyprotecting operating system 128 and other programs from program errors.One embodiment of the present invention supports VTU 138 memory accessin kernel, user, and supervisor addressing modes. This allowsapplication programs to bypass operating system 128 to access VBP 208,thereby reducing use of processing resources and overhead associatedwith accessing memory. Other embodiments of the present invention may beused in computer systems that support additional, or fewer, privilegelevels.

FIG. 3 shows memory address space for one embodiment of processor 102.For 32-bit addressing mode, memory address space 300 includes kernelmemory segments 302, 304, and 306, supervisor memory segment 308, anduser memory segment 310. In 64-bit addressing mode, memory address space312 includes kernel memory segments 314, 316, 318, 320, and 322,supervisor memory segments 324 and 326, user memory segment 328, andaddress error segments 330, 332, and 334. In virtual mode, preselectedbits in a status register determine whether processor 102 is operatingin a privileged mode such as user, supervisor, or kernel. Additionally,memory addressing mode is determined by decoding preselected bits of thevirtual address. In one embodiment of the present invention, forexample, bits 29, 30, and 31 in 32-bit addressing mode, and bits 62 and63 in 64-bit addressing mode, are used to select user, supervisor, orkernel address spaces. In this embodiment, all accesses to thesupervisor and kernel address spaces generate an address error exceptionwhen processor 102 is operating in user mode. Similarly, when processor102 is operating in the supervisor mode, all accesses to the kerneladdress space generate an address error exception. It is important tonote that the foregoing description is one type of processing systemwith which the present invention may be utilized, and that the presentinvention may also be utilized in a variety of other processing systemshaving different memory modes, privilege levels, and logic forcontrolling access to memory.

In computer systems known in the prior art, specific bits in the TLBdetermine whether virtual memory accesses will be cached when theprocessor is fetching code or data from mapped memory space. Forunmapped accesses, the cacheability is determined by the address itself.In the memory segments shown in FIG. 3, for example, accesses to kernelsegment 304 (or 316 in 64-bit mode) space are always uncached. Bits59-61 of the virtual address determine the cacheability and coherencyfor memory segment 322. Cache memory 136 can be disabled for accesses tomemory segment 306 (or 318 in 64-bit mode) space by using bits in aconfiguration register.

In the present invention, all accesses generated by VTU 138 bypass cachememory 136. Thus, VTU 138 regards the entire memory space as beinguncached and the TLB bits, or the bits in the configuration registerwhich control access to cache memory 136, are ignored.

To preserve binary compatibility among different models and generationsof processors 102, configuration information such as the size of vectorbuffer pool 208 in VTU 138, the number of buffers, and the maximumstream size, is stored in a location in processor 102. Applicationprograms 132 read the configuration information and configure themselvesfor data transfers based on the configuration information. Thissemi-dynamic allocation mechanism provides a flexible implementation ofthe present invention that is usable in various processors.

Alternatively, a more complex, fully dynamic mechanism may be utilizedin which the allocation is completely carried out by the processor, andapplication program 132 has no control on which buffer is allocated to avector stream. Processor 102 returns a buffer identification number witha vector load instruction and the program uses the identification numberto point to the stream. Note that in either embodiment, each vectorbuffer is used by one program and each program uses only one buffer.

In one embodiment of the present invention as shown in FIG. 4,configuration register 400 contains configuration information and statusbits for VTU 138. It is important to note that configuration register400 may contain as many bits as required to represent the configurationinformation, and different fields in addition to or instead of thoseshown in FIG. 4 may be used. Configuration register 400 may reside inVTU 138 or in another location in computer system 100.

In the example shown in FIG. 4, Buffer Size (BS) in bits 0 through 2represents the length of vector buffers 214, 216, 218. In oneembodiment, the bits are set in various combinations to representdifferent buffer lengths, for example, bit 0 set to zero, bit 1 set tozero, and bit 2 set to zero represents buffer length(s) of twokilobytes, whereas bit 0 set to 1, bit 1 set to one, and bit 2 set tozero represents buffer length(s) of 16 kilobytes.

Vector buffer pool size (VBP_S) in bits 3 through 6 represents thenumber of buffers in vector buffer pool 208.

Vector buffer identification (VB_ID) in bits 7 through 10 represents theidentification of the active buffer. It defaults to zero and can only bemodified by a program having the appropriate level of privilege tochange the parameter, such as the kernel of operating system 128.

In this embodiment, bits 11, bit 12, and bits 16 through 29 arecurrently not utilized. These bits could be used by other embodiments,or to expand capabilities for the present embodiment.

Bits 13 through 15 represent the code for the exception caused by VTU.If an exception is generated by VTU, the exception processing routinecan decode these bits to determine the cause of the exception. Forexample, a value zero on these bits represents the VTU Inaccessibleexception and a value of one signifies an Invalid Buffer AddressException. Both will be explained later in the discussion regarding VTUinstructions hereinbelow.

Vector buffer pool in-use (VBI) in bit 30 indicates whether vectorbuffer pool 208 is free or in-use.

Vector Buffer Pool Lock (VBL) in bit 31 indicates whether vector bufferpool 208 is allocated to a program or available for use by a program.

Address Space Protection

A technique known in the art as “paging” is used in computer system 100where physical memory is divided in blocks (pages) of a fixed size.Physical address space is directly addressable while logical addressspace is the set of abstract locations addressed by a program. A memorymap translates logical address space to physical address space. Thelogical address space may be discontinues and larger than the physicaladdress space. Only a portion of the logical address space is broughtinto the physical address space at a time.

When processor 102 is accessing memory in a mapped space, the vectorstream which is being transferred must be contained entirely within asingle virtual page. If a stream is allowed to cross a virtual pageboundary, the memory locations accessed by the stream may not becontiguous in the physical memory, as each virtual page could be mappedto any physical page.

In one embodiment of the present invention, memory 210 is DRAM. Toaddress a location in DRAM memory 210, the physical address ispartitioned into a row and a column address, which are sequentiallypresented to the DRAM memory controller 222. The row address determinesthe DRAM page and the column address points to a specific location inthe DRAM page (the page mode access). The performance of memory 210depends mainly on the latency in the row access and the data rate in thecolumn access. In recent DRAM architectures, if consequent accesses fallin the same DRAM page of memory 210, the row address is provided onlyfor the first access and it is latched for the succeeding accesses.Since the latency of a row access is longer than a page mode access,this mechanism greatly improves the performance for burst accesses tosequential vector-like data sets by amortizing the row access latencyover the page mode accesses.

To ensure that a vector stream does not cross a virtual page boundary,processor 102 determines whether both the beginning and ending addressesfall within the same virtual page of memory 210. Since VTU 138 isprovided only with the starting address, the stream length, and thestride, processor 102 calculates the ending address by multiplying thevector length by the stride and adding the result to the startingaddress (taking into account the appropriate data width) according tothe following equation:Address of last entry =((Stream length−1)*Stride*Data width)+Address offirst entry

In another embodiment of the present invention, the size of the streamsare restricted to powers of two, which allows the multiplication to becarried out by shifting the stride. The amount of shift is determined bythe stream length. When data width is a power of two, the secondmultiplication inside the parentheses will be a shift operation. Theabove equation may thus be restated as:Address of last entry=(Stream Length*Stride*Data Width)+(Address offirst entry−[Stride*Data Width])

All multiplications in the above equation can be performed by usingshift operations. The first and second parentheses can be evaluated inparallel and their results added to calculate the address of the lastentry of the stream.

Compiler

In order to take advantage of the capabilities for handling transfers ofvector data using VTU 138, the present invention utilizes a compilerthat identifies statements within a program which would benefit fromblock data transfers to and from processor 102. As each program iscompiled, the compiler looks for loops which contain operations usingarrays. Candidate loops include, but are not limited to, those where theindices to the array have a constant stride and offset, (e.g., for(i=x;i<y; i+=step)), there are no conditional statements in the loop whichalter the pattern of vector data flow, and, where the loop trip countcan be determined during compilation, a loop trip count that is largeenough to result in a performance gain after accounting for theoverhead, if any, associated with setting up the array in VTU 138.Relevant loops can also be identified by the user before compilation,such as by using a special instruction recognized by the compiler.

Once the code is identified, the loop needs to be divided in a series ofblocks to be processed through vector buffers 214, 216, 218. The vectordata used by each iteration of the loop is allocated to differentstreams in the buffer. The compiler uses instructions that allow thedata to be handled by VTU 138 in a series of stream loads and stores.

Compiler Instructions

The compiler utilized with the present invention includes severalcompiler instructions that apply to handling vector buffer pool 208 inVTU 138 including load vector, store vector, move vector from buffer,move vector to buffer, synchronize vector transfer, and free vectorbuffer.

The load vector instruction, denoted by LDVw in one embodiment, loads avector from memory 210 to a vector buffer, such as one of buffers 214,216, or 218. The LDVw instruction contains the 32-bit or 64-bit(depending on the addressing mode) virtual memory address for the firstvector element, the starting vector buffer address, the length of thevector stream (restricted to a power of two such as 2, 4, 8, 16, or 32),and the stride of the vector stream (i.e, the distance between eachentry in memory 210). To use this embodiment of the LDVw instruction,the following syntax is used:LDVw R_(S), R_(T)where:

-   -   R_(S) is the virtual memory address for the first vector        element; and    -   R_(T) is a set of fields including the starting vector buffer        address, the length of the vector stream, and the stride of the        vector stream.

The format of one embodiment of the LDVw instruction is: Bits Bits Bits31-26 25-21 20-16 Bits 15-13 Bits 12-11 Bits 10-6 Bits 5-0 COP2 R_(S)R_(T) 000 W₁ W₀ 00000 LDV 010010 101000where:

-   -   COP2 is a label for a major opcode (010010) relating to vector        and multimedia data;    -   LDV is a label for a minor opcode (101000) for the load vector        instruction; and

W₁ and W₀ bits in the instruction determine the width of the data beingtransferred, as follows: Instruction W₁ W₀ Data Width LDVB 00 Byte LDVH01 Half Word (2 bytes) LDVW 10 Word (4 bytes) LDVD 11 Double word (8bytes)

The format of one embodiment of R_(T) is: Bits 63-48 Bits 47-35 Bits34-32 Bits 31-0 Stride xxx xxxx xxxx Length Buffer Starting Address

There are several exceptions that may be raised with this instructionwhen an invalid or erroneous operation is attempted. In one embodiment,a first exception that may be raised is the TLB refill exception whichindicates that a virtual address referenced by the LDV instruction doesnot match any of the TLB entries. Another exception is the TLB invalidexception that indicates when the referenced virtual address matches aninvalid TLB entry. A third exception that may be raised is the BussError exception that indicates when a bus error is requested by theexternal logic, such as included in memory controller 222, to indicateevents such as bus time out, invalid memory address, or invalid memoryaccess type. A fourth exception is the Address Error exception whichindicates that the referenced virtual address is not aligned to a properboundary.

The exceptions listed in the preceding paragraph are typical of standardexceptions that are implemented in many different computer processorarchitectures. In one embodiment of VTU 138, additional types ofexceptions relating to one or more of the vector transfer instructionsare also implemented. For example, the Invalid Buffer Address exceptionmay be implemented to indicate that the buffer address referenced by theLDV instruction is beyond the actual size of the buffer. Anotherexception that is specifically implemented in VTU 138 is the VTUInaccessible exception that indicates that the VBL bit in the VTUcontrol register is set and a VTU instruction is being executed.

The next VTU instruction that is implemented is the store vectorinstruction, denoted in one embodiment by STVw, which stores a vectorfrom a vector buffer, such as one of buffers 214, 216, or 218, to memory210. The STVw instruction contains the 32-bit or 64-bit (depending onthe addressing mode) virtual memory address for the first vectorelement, the starting vector buffer address, the length of the vectorstream (restricted to a power of two such as 2, 4, 8, 16, or 32), andthe stride of the vector stream (i.e, the distance between each entry inmemory 210). To use this embodiment of the STVw instruction, thefollowing syntax is used:STVw R_(S), R_(T)where:

-   -   R_(S) is the virtual memory address for the first vector        element; and    -   R_(T) is a set of fields including the starting vector buffer        address, the length of the vector stream, and the stride of the        vector stream.

The format of one embodiment of the STVw instruction is: Bits Bits Bits31-26 25-21 20-16 Bits 15-13 Bits 12-11 Bits 10-6 Bits 5-0 COP2 R_(S)R_(T) 000 W₁ W₀ 00000 STV 010010 101001where:

-   -   COP2 is a label for a major opcode (010010) relating to vector        and multimedia data;    -   STV is a label for a minor opcode (101001) for the store vector        instruction; and

W₁ and W₀ bits in the instruction determine the width of the data beingtransferred, as follows: Instruction W₁ W₀ Data Width STVB 00 Byte STVH01 Half Word (2 bytes) STVW 10 Word (4 bytes) STVD 11 Double word (8bytes)

The format of one embodiment of R_(T) is: Bits 63-48 Bits 47-35 Bits34-32 Bits 31-0 Stride xxx xxxx xxxx Length Buffer Starting Address

As with the LDV instruction, there are several exceptions that may beraised with the STV instruction when an invalid or erroneous operationis attempted including the TLB refill exception, the TLB invalidexception, the Bus Error exception, the Address Error exception, theInvalid Buffer Address exception, and the VTU Inaccessible exception, asdescribed hereinabove for the LDV instruction.

The next VTU instruction, the move vector from buffer instruction,denoted in one embodiment by MVF.type.w, transfers a vector from avector buffer, such as one of buffers 214, 216, or 218, to register file220. The entry point in the vector buffer pointed to by the contents ofregister R_(S) is loaded into the R_(T) register. Depending on the type,R_(T) represents an integer or floating-point register. The data in thevector buffer must be on its natural boundary. To use this embodiment ofthe MVF.type.w instruction, the following syntax is used:MVF.type.w R_(S), R_(T)where:

-   -   type indicates format such as integer or floating point;    -   w determines the width of the data being transferred;    -   R_(S) is the virtual memory address for the starting entry in        the vector buffer;    -   R_(T) is an integer or floating point register, depending on        type.

The format of one embodiment of the MVF.type.w instruction is: Bits BitsBits 31-26 Bits 25-21 Bits 20-16 15-14 Bit 13 12-11 Bits 10-6 Bits 5-0COP2 R_(S) R_(T) 000 Integer/ W₁ W₀ 00000 MVF 010010 Floating- 101010Pointwhere:

-   -   COP2 is a label for a major opcode (010010) relating to vector        and multimedia data;    -   MVF is a label for a minor opcode (101010) for the move vector        from buffer instruction; and

W₁ and W₀ bits in the instruction determine the width of the data beingtransferred, as follows: Instruction W₁ W₀ Data Width MVF.type.B 00 ByteMVF.type.H 01 Half Word (2 bytes) MVF.type.W 10 Word (4 bytes)MVF.type.D 11 Double word (8 bytes)

The Invalid Buffer Address exception, and the VTU Inaccessibleexception, as described hereinabove for the LDV instruction, areimplemented in VTU 138 for use with the MVF instruction.

The move vector to buffer instruction, denoted in one embodiment byMVT.type.w, transfers a data element to a vector buffer, such as one ofbuffers 214, 216, or 218, from register file 220. The least significantportion of register R_(T) is transferred into the vector buffer entrypointed to by the contents of register R_(S). Depending on the type,R_(T) represents an integer or floating-point register. The data in thevector buffer must be on its natural boundary. To use this embodiment ofthe MVT.type.w instruction, the following syntax is used:MVT.type.w R_(S), R_(T)where:

-   -   type indicates format such as integer or floating point;    -   w determines the width of the data being transferred;    -   R_(S) is the address for the entry in the vector buffer;    -   R_(T) is an integer or floating point register, depending on        type.

The format of one embodiment of the MVT.type.w instruction is: Bits31-26 Bits 25-21 Bits 20-16 Bits 15-14 Bit 13 Bits 12-11 Bits 10-6 Bits5-0 COP2 R_(S) R_(T) 000 Integer/ W₁ W₀ 00000 MVT 101011 010010Floating- Pointwhere:

-   -   COP2 is a label for a major opcode (010010) relating to vector        and multimedia data;    -   MVT is a label for a minor opcode (101011) for the move vector        from buffer instruction; and

W1 and W₀ bits in the instruction determine the width of the data beingtransferred, as follows: Instruction W₁ W₀ Data Width MVT.type.B 00 ByteMVT.type.H 01 Half Word (2 bytes) MVT.type.W 10 Word (4 bytes)MVT.type.D 11 Double word (8 bytes)

The Invalid Buffer Address exception, and the VTU Inaccessibleexception, as described hereinabove for the LDV instruction, are alsoused with the MVT instruction.

Another instruction unique to VTU 138 is the synchronize vector transferinstruction, denoted in one embodiment by SyncVT, ensures that any VTU138 instructions fetched prior to the present instruction are completedbefore any VTU 138 instructions after this instruction are allowed tostart. SyncVT blocks the issue of vector transfer instructions until allprevious vector transfer instructions (STVw, LDVw) are completed. Thisinstruction is used to synchronize the VTU 138 accesses withcomputation. To use this embodiment of the SyncVT instruction, thefollowing syntax is used:SyncVT

The format of one embodiment of the SyncVT instruction is: Bits 31-26Bits 25-6 Bits 5-0 COP2 0000 0000 0000 0000 0000 SyncVT 010010

The free vector buffer instruction, denoted in one embodiment by FVB, isused to make the active vector buffer in vector buffer pool 208accessible to other programs. The instruction clears the vector bufferin-use (VBI) bit in configuration register 400. Bits 31-26 Bits 25-6Bits 5-0 COP2 0000 0000 0000 0000 0000 FVB 010010 101100

The VTU Inaccessible exception, as described hereinabove for the LDVinstruction, can also be generated by the FVB instruction.

Vector Buffer Pool (VBP)

In one embodiment, VBP 208 is SRAM which is partitioned into fixed-sizedvector buffers. The SRAM may be dual port RAM where data can be read andwritten simultaneously in the memory cells. In another embodiment, VBP208 includes parity bits for error detection in buffers 214, 216, and218. The compiler allocates one or more buffers 214, 216, 218 to eachprogram, and partitions each buffer 214, 216, 218 into variable-sizedvector streams. Another embodiment of VBP 208 includes only onedual-ported SRAM vector buffer that is allocated to one program at atime. The dual-ported SRAM allows one stream to be transferred betweenVBP 208 and memory 210 while elements from another stream are moved toregister file 220 for computation or the result of a specificcomputation updates another stream. The present invention may alsoutilize multiple buffers in VBP 208, thereby enabling a wider variety ofimplementations.

In another embodiment, two single-port SRAM banks may be substituted fordual-port SRAM in one or more of buffers 214, 216, 218. Only certaintypes of programs can be accelerated using single-port SRAM, however,such as programs requiring a contiguous vector buffer for doingmultilevel loop nests (e.g. matrix multiply), data re-use (e.g. infiniteimpulse response (IIR) filters), and data manipulation (e.g. rotation).Two single-port vector buffers may also be used advantageously withother sets of program instructions, such as a fast, local SRAM forlook-up tables.

Vector Transfer Execution Unit

VTU 138 is implemented to execute in parallel with cache memory 136. Onone side, VTU 138 interfaces to memory controller 222, and on the otherside it is connected the processor core that includes register file 220and vector transfer execution unit 206. This configuration achieves highthroughput on memory bus 224 by performing vector transfers andexecuting program instructions using vector data without blocking thepipeline.

The compiler transfers vector streams between VBP 208 and memory 210 byusing load vector (LDVw) and store vector (STVw) instructions. Thevariable w indicates the width of the data to be transferred, such as bfor bytes, h for half-words, w for words, and d for double-words. Eachinstruction uses four operands specified in two registers. The startingvirtual address of the stream is provided in one register, and thevector buffer address, stream length, and stride are all stored in asecond register.

When the data is loaded into one of buffers 214, 216, and 218, it can betransferred to register file 220 in processor 102 through MVF.type andMVT.type instructions, where the “type” bit in these instructionsdetermines whether the target register for the instruction is an integeror a floating-point register. These instructions are similar to regularload and store, however they operate on buffers 214, 216, and 218 ratherthan memory 210.

A synchronization instruction, SyncVT, is used to ensure that any VTUinstructions fetched prior to the present instruction are completedbefore any VTU instructions after this instruction are allowed to start,and to synchronize accesses to memory 210 by VTU 138 with computation. Atypical portion of pipelined code sequence may appear as: LDV <stream1>LDV <stream2> SyncVT LDV <stream3> LDV <stream4>  <streamA> =ƒ(<stream1>, <stream2>) SyncVT STV <streamA> LDV <stream5> LDV <stream6> <streamB> = ƒ(<stream3>, <stream4>)

If the program instructions including VTU instructions are issuedsequentially in order, when a SyncVT instruction is used, it could blockthe issue of all instructions and not just the vector transferinstructions. By judicious code relocation, the compiler can alter theplacement of the SyncVT instructions so as not to block the processorunnecessarily. Thus, in the present invention, when burst instructions(i.e., instructions that transfer streams of data between memory 210 anda vector buffer) are issued, their execution does not block theexecution of other instructions.

When a vector transfer stream instruction (LDVw or. STVw) is issued, VTU138 performs a TLB access on the starting address of the stream which isprovided by the instruction. While the virtual-to-physical addresstranslation is being performed, VTU 138 verifies that the ending addressof the stream does not fall in another virtual page. If the streamcrosses a page boundary, an address error exception is generated. Afterthe address translation, the instruction is posted to vector transferinstruction queue (VTIQ) 226. The vector instructions posted in VTIQ 226are executed in order independent of the instructions in the processorpipeline. When a SyncVT instruction reaches the issue stage, it stopsthe issue of all vector transfer unit instructions until all VTUinstructions have been executed.

Vector Buffer Ownership

VBP 208 is partitioned into one or more vector buffers 214, 216, 218which can be allocated to different programs. Processor 102 only allowsone vector buffer to be active at a time, and allocation of the vectorbuffers 214, 216, and 218 is carried out by operating system 128 usingeach program's ASID.

In the present invention, operating system 128 allocates VBP 208 amongmultiple programs. FIG. 5 illustrates how ownership of VBP 208 ismanaged during a context switch (i.e., when switching execution from oneapplication program 502 to another application program 504). VBP 208 isaccessed only by one program at a time, however, kernel 506 or operatingsystem 128 can always access VBP 208 and overwrite the access-right ofanother program to VBP 208. The vector buffer lock (VBL) and vectorbuffer in-use (VBI) bits in configuration register 400 control accessrights to the active buffer in VBP 208. Note that VTIQ 226 is used onlyby one program at a time and kernel 506 must empty this queue (executeall VTU instructions in the queue) before another program is allowed touse VTU 138.

When bit VBL is zero, the current program can access the active vectorbuffer in VBP 208 through VTU instructions. If the VBL bit is set,execution of any VTU instruction will cause a VTU inaccessibleexception. In that case, kernel 506 can decide whether and how bit VBLwill be cleared and execution is switched back to the VTU instructionwhich caused the exception. If the active vector buffer is in use by aprogram, bit VBL is set when an interrupt (including context switching)takes place. This bit can also be modified by kernel 506 using anappropriate instruction. When a program accesses VBP 208 successfully,bit VBI is set. Bit VBI will be set until cleared by the applicationprogram using it. As shown in block 508, bit VBI can be cleared by usinganother VTU instruction, known in one embodiment as free vector buffer(FVB). Similar to all the other VTU instructions, the FVB instructioncan be executed only if bit VBL is cleared, or by kernel 506. Otherwise,a VTU inaccessible exception will be generated.

When processor 102 is reset, both VBL and VBI bits are cleared. Kernel506 can use the active vector buffer at any time and bits VBL and VBIare ignored. Issue of the first vector transfer instruction by a programcauses bit VBI to be set as shown in block 510. When context switch 512takes place, bit VBL is set as shown in block 514, which prevents secondapplication program 504 from accessing VBP 208. When bit VBL is set, novector transfer instructions are executed out of VTIQ 226 as shown inblock 514. Kernel 506 stores the ASID of the previous program (ID of theactive vector buffer owner), and performs context switch 516 to secondapplication program 504.

When second application program 504 attempts to access VBP 208 by usinga VTU instruction, a VTU inaccessible exception is generated since bitVBL is set as shown in block 518. At this point, control transfers tokernel 506 (context switch 520), and, depending on the availability ofbuffers 214, 216, 218 in VBP 208, kernel 506 can empty VTIQ 226 eitherby executing a SyncVT instruction followed by switching the activevector buffer and performing context switch 522 to second applicationprogram 504, or by blocking second application program 504 andperforming context switch 524 back to first application program 502.Before performing context switch 524 back to first application program502, kernel 506 checks the ASID of first application program 502 withthe stored ASID, and, if they match, kernel 506 sets bit VBI, andswitches the execution back to first application program 502. When firstapplication program 502 is finished using VTU 138, SyncVT and FVBinstructions are issued, and bit VBI is cleared as shown in block 508.

If kernel 506 alternatively performs context switch 522, secondapplication program 504 resumes execution until finished. Beforeperforming context switch 528, second application program 504 issuesSyncVT and FVB instructions, and bit VBI is cleared, as shown in block528. Since bit VBI is cleared, bit VBL will be cleared during contextswitch 524 to first application program 502.

Bus Architecture

Memory bus 224 provides burst transfers required by VTU 138. In oneembodiment, the protocol for memory bus 224 is a 64-bit, asynchronousprotocol that can accommodate burst transfers of variable sizes. In thisprotocol, the end of the data transfer is signaled by any logic deviceconnected to processor 102 that receives requests from processor 102.Such a logic device is also referred to as an external agent.

If the data associated with a stream is located in contiguous locationsin memory 210 or if the width of the data entries is equal to the widthof memory bus 224, VTU transfer instructions transfer the data utilizingthe entire bandwidth of memory bus 224. However, for streams whose dataelements are smaller than the width of memory bus 224, and the stridebetween their data elements is larger than one, each transfer on memorybus 224 would carry data which is smaller than the width of bus 224,resulting in suboptimal usage of memory bus 224.

For such cases, it is possible that memory controller 222 can pack twoor more data elements into a larger block which would use memory bus 224more efficiently. As an example, FIG. 6a shows that four word dataelements 602, 604, 606, 608 require four separate transfers 610, 612,614, 616 when data elements 602, 604, 606, 608 are not combined, whereasFIG. 6 b shows that only two transfers 618, 620 are required when theelements are packed in doubleword packages 622, 624. The protocol formemory bus 224 implements such a capability by allowing packing ratiosof 1, 2, 4, and 8. The maximum block size which is transferred in oneinstance on memory bus 224 is 8 bytes wide, therefore, not all packingratios can be used with all data widths. The possible packing ratios foreach data width is as follows: Possible Data Width Packing Ratios Byte1, 2, 4, 8 Halfword 1, 2, 4 Word 1, 2 Double Word 1

Thus, for data sizes less than a double word, if the data elements arenot laid out contiguously in memory 210 (i.e., stride is greater thanone (1)), the possible data packing ratios are 1, 2, 4, and 8. It isimportant to note that another memory bus 224 may be utilized with thepresent invention that have a width that is different from 64 bits. Thepossible data packing ratios would therefore vary accordingly.

Information about the size of the burst, its stride, and the implementedpacking ratio is conveyed from processor 102 to the external agent. Thecapability to read and write bytes (8 bits) in VBP 208 is requiredregardless of the implemented width vector buffer 214. In one embodimentof the present invention, therefore data in vector buffers 214, 216, 218are aligned on a natural boundary (e.g. a double-word is aligned on an8-byte address boundary).

Burst Transactions

FIG. 7 shows a timing diagram 700 for a variable-length vector burst. Inone embodiment, memory bus 224 includes a 64-bit unified address anddata (SysAD) bus 702, a 9-bit command (SysCmd) bus 704, and handshakingsignals SysClk 706, ValidOut 708, and ValidIn 710. SysAD bus 702 andSysCmd bus 704 are bi-directional, i.e., they are driven by processor102 to issue a processor request, and by an external agent to issue anexternal request. On SysAD bus 702, the validity of the addresses anddata from processor 102 is determined by the state of ValidOut signal708. Similarly, validity of the address and data from the external agentis determined by ValidIn signal 710. SysCmd bus 704 provides the commandand data identifier for the transfer.

To provide variable-sized transfers, two new burst read and burst writecommands are provided with the list of other known commands on SysCmdbus 704. When a burst read or burst write cycle is initiated during theaddress cycle, the starting address, burst length, and stride areprovided to the external agent on SysAD bus 702. The external agent canlatch this information with the address.

A stream is not necessarily required to be contained within a page ofDRAM memory 210 for computer system 100 according to the presentinvention to operate correctly. If a stream crosses a DRAM page boundaryin memory 210, there is an interruption in the burst transfer from theexternal agent to processor 102 and vice versa. The performance of VTU138 will degrade if the number of streams crossing one or more pages ofmemory 210 becomes considerable relative to the total number of memoryaccesses. SysAD bus 702 determines if an interruption in the datatransfer has occurred based on the state of the ValidIn signal 710 orValidOut signal 708.

To gain maximum efficiency in burst accesses, the stream which istransferred should be completely contained in one memory page toeliminate page change latencies. In one embodiment of the presentinvention, a fixed number of vector buffer bytes, such as 4096 bytes(512 doublewords), are allocated to every application program 132. Thepresent invention may be implemented so that only one applicationprogram 132 has access to VBP 208 at a time and therefore VBP 208contains one vector buffer 214 having a predetermined number of bytes.Different bit combinations in configuration register 400 are used tospecify vector buffer size. Additional vector buffers 214, 216, 218 canbe provided to allow one or more vector buffers to be allocated amongmultiple application programs 132.

The present invention advantageously provides concurrent (pipelined)memory transfer bursts and processor computation, and both read andwrite burst transfers with variable stride through memory. The presentinvention also allows application programs 132 to hold data in vectorbuffers 214, 216, 218 to exploit temporal locality of vector data.

Application programs 132 that handle large amounts of vector data, suchas multimedia processing, large block of vector data comprise a majorportion of the data used by the program. Performance of D-cache 204 isgreatly enhanced with the present invention since VTU 138 offloadsD-cache 204 from handling large blocks of vector data. Using VTU 138,each vector can reside in any page and the cost of switching pageboundaries is amortized over the entire transaction by using long bursttransfers. At the application level, the compiler can extract vectorstreams and exercise an efficient scheduling mechanism to achieveperformance improvements. Additionally, scatter/gather operations can beimplemented in the present invention by allowing both read andwrite-back bursts which stride through memory 210. In contrast, D-cache204 line fill mechanisms can only implement unit stride transfersefficiently.

While the invention has been described with respect to the embodimentsand variations set forth above, these embodiments and variations areillustrative and the invention is not to be considered limited in scopeto these embodiments and variations. For example, the vectorinstructions may have different names and different syntax than thevector instructions that were discussed hereinabove. Accordingly,various other embodiments and modifications and improvements notdescribed herein may be within the spirit and scope of the presentinvention, as defined by the following claims.

1-30. (Cancelled).
 31. A compiler for handling vector data in anapplication program, comprising: a source code parser for identifyinguse of vector data in the application program; an object code generatoroperable to implement at least one vector data instruction fortransferring the vector data between a memory and a buffer when thesource code parser identifies the use of vector data, the object codegenerator being further operable to implement a synchronizationinstruction to synchronize accessing the vector data with processing thevector data when the application program is executing.
 32. The compilerof claim 31 wherein the at least one vector instruction transfers datafrom the memory to the buffer.
 33. The compiler of claim 31 wherein theat least one vector instruction transfers data from the buffer to thememory.
 34. The compiler of claim 31 wherein the at least one vectorinstruction transfers data from the buffer to a general purposeregister.
 35. The compiler of claim 31 wherein the at least one vectorinstruction transfers data from a general purpose register to thebuffer.
 36. The compiler of claim 31 wherein the at least one vectorinstruction is used to determine whether the buffer is available foruse.
 37. The compiler of claim 31 wherein the at least one vectorinstruction includes information about a vector stream including thestarting address of the vector stream, and the length of the vectorstream.
 38. The compiler of claim 31 wherein the at least one vectorinstruction includes information about a vector stream including thestride of the vector stream, and the starting address of the buffer. 39.The compiler of claim 31 wherein the at least one vector instructionincludes information about a vector stream including the width of thevector data in the data stream.
 40. The compiler of claim 31 wherein theat least one vector instruction includes information about whether thevector data is integer or floating point data.
 41. A method comprising:a compiler scheduling a transfer of a first stream of vector databetween a processor and a memory; and the compiler scheduling a transferof a second stream of vector data between the processor and the memoryso that the second stream of vector data is transferred while data ofthe first stream is processed.
 42. A computer-readable medium havingstored thereon instructions which, when executed by a processor,configure the processor to: schedule a first transfer of a first streamof vector data between the processor and a memory; and schedule a secondtransfer of a second stream of vector data between the processor and thememory such that the second transfer occurs while data of the firststream of vector data is processed by the processor.
 43. Thecomputer-readable medium of claim 42 which further configures theprocessor to: schedule the first transfer of the first stream of vectordata between a vector buffer of the processor and the memory; andschedule the second transfer of the second stream of vector data betweenthe vector buffer and the memory such that the second transfer occurswhile data of the first stream of vector data is processed by theprocessor.
 44. The computer-readable medium of claim 43 wherein at leastone of the first transfer and the second transfer is a burst transfer.45. The computer-readable medium of claim 43 which further configuresthe processor to: partition vector data of a computer program into aplurality streams.
 46. The computer-readable medium of claim 42 whichfurther configures the processor to: detect vector data in a computerprogram.
 47. The computer-readable medium of claim 46 which furtherconfigures the processor to: detect a vector data indicator in thecomputer program, the vector data indicator identifying the vector data.48. The computer-readable medium of claim 46 which further configuresthe processor to: generate a vector instruction, wherein a stream of theplurality of streams is transferred from the memory to the vector bufferin response to execution of the vector instruction.
 49. Thecomputer-readable medium of claim 46 which further configures theprocessor to: generate a vector instruction, wherein a stream of theplurality of streams is transferred from the vector buffer to the memoryin response to the execution of the vector instruction.
 50. Thecomputer-readable medium of claim 46 which further configures theprocessor to: generate a vector instruction, wherein a stream of theplurality of streams is transferred from the vector buffer to a registerof the processor in response to the execution of the vector instruction.51. The computer-readable medium of claim 46 which further configuresthe processor to: generate a vector instruction, wherein a stream of theplurality of streams is transferred from a register of the processor tothe vector buffer in response to the execution of the vectorinstruction.
 52. The computer-readable medium of claim 42 which furtherconfigures the processor to: generate a synchronization instruction tosynchronize the first and second transfers while the data of the streamof vector data is processed by the processor.